Memory system and soc including linear addresss remapping logic

ABSTRACT

A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 13/803,269, field on Mar. 14, 2013, which claims the benefit ofKorean Patent Application No. 10-2012-0065624 filed Jun. 19, 2012, inthe Korean Intellectual Property Office, the entire contents of whichare hereby incorporated by reference.

BACKGROUND

The inventive concepts described herein relate to a memory system, andmore particularly, relate to memory system and a system on a chip (SoC)including linear address remapping logic.

A memory system may commonly include two or more processors. Forexample, a mobile system may include a modem and an applicationprocessor, or multimedia processor. The memory system including two ormore processors may necessitate at least two or more memory devices inorder to service the multiple processors independently.

In the above example, the modem may be accompanied by a NOR flash memoryto be used as code storage and a DRAM to be used for execution of code.The application processor may be accompanied by a NAND flash memory forthe storage of code and data as well as a DRAM for the execution ofcode. Code and data may be transferred between the modem and theapplication processor through an UART (Universal Asynchronous ReceiverTransmitter), SPI (Serial Peripheral Interface), or SRAM interface.

Meanwhile, for supporting the operation of the mobile system, the memorysystem may perform a data interleaving operation through two or moreDRAMs. In such an interleaving operation, the memory system mayalternately access two or more DRAMs. This has the effect of improvingsystem performance.

SUMMARY

Current memory systems that employ interleaving as a way to improveperformance can also consume relatively more power. In some situations,it may be possible to access only a single DRAM for performing anoperation, rather than multiple DRAMs, with minimal or no adverse effecton system performance. In such situations, it may be more advantageousto use a linear access method, rather than an interleaving method.Methods and systems of the present inventive concepts provide forefficient use of power in memory systems that employ multiple memorydevices.

In accordance with embodiments of the inventive concepts, asystem-on-chip connected to a first memory device and a second memorydevice, comprises: a memory controller configured to control aninterleaving access operation on the first and second memory devices; amodem processor configured to provide an address for accessing the firstor second memory devices; and a linear address remapping logicconfigured to remap an address received from the modem processor and toprovide the remapped address to the memory controller, wherein thememory controller performs a linear access operation on the first orsecond memory device in response to receiving the remapped address.

In some embodiments, the linear address remapping logic receives anaddress from the modem processor, remaps an address of the modemprocessor selectively in response to a control signal, and provides theremapped address to the memory controller.

In some embodiments, the remapped address is partitioned into aninterleaving access area and a linear access area, wherein the remappingof the address operation performed by the linear address remapping logicis accomplished by changing a location of a most significant bit of thelinear access area.

In some embodiments, the linear address remapping logic determineswhether an address input from the modem processor belongs to the linearaccess area, based on a base address and a size of the linear accessarea.

In some embodiments, the linear address remapping logic decides theaddress input from the modem processor to belong to the linear accessarea when the address input from the modem processor is equal to orgreater than the base address of the linear access area and less than asum of the base address and the size of the linear access area.

In some embodiments, the linear address remapping logic decides theaddress input from the modem processor to belong to the interleavingaccess area when the address input from the modem processor is less thanthe base address of the linear access area or equal to or greater than asum of the base address and the size of the linear access area.

In accordance with embodiments of the inventive concepts, a method ofaccessing first and second memory devices connected to a system-on-chip,comprises: receiving an address for accessing the first or second memoryfrom a modem processor of the system-on-chip; determining whether theaddress corresponds to an interleaving access area or to a linear accessarea; and performing a linear access operation or an interleaving accessoperation on the first and second memory devices according to thedetermination result.

In some embodiments, the system-on-chip further comprises linear addressremapping logic which is configured to remap an address received fromthe modem processor and to provide the remapped address to a memorycontroller.

In some embodiments, the remapped address is partitioned into aninterleaving access area and a linear access area and wherein theremapping of the address operation performed by the linear addressremapping logic is performed by changing a location of a mostsignificant bit of the linear access area.

In some embodiments, the linear address remapping logic determineswhether an address input from the modem processor belongs to the linearaccess area, based on a base address and a size of the linear accessarea.

In accordance with embodiments of the inventive concepts, a memorysystem comprises: a memory controller configured to control aninterleaving access operation on the first and second memory devices; amodem processor configured to provide an address for accessing the firstor second memory device; and linear address remapping logic configuredto remap an address received from the modem processor to provide theremapped address to the memory controller, wherein the memory controllerperforms a linear access operation on the first or second memory devicein response to receiving the remapped address.

In some embodiments, the remapped address is partitioned into aninterleaving access area and a linear access area.

In some embodiments, an address remapping operation of the linearaddress remapping logic is performed by changing a location of a mostsignificant bit of the linear access area.

In some embodiments, the linear address remapping logic determineswhether an address input from the modem processor belongs to the linearaccess area, based on a base address and a size of the linear accessarea.

In some embodiments, the linear address remapping logic decides theaddress input from the modem processor to belong to the linear accessarea when the address input from the modem processor is equal to orgreater than the base address of the linear access area and less than asum of the base address and the size of the linear access area.

In some embodiments, the linear address remapping logic decides theaddress input from the modem processor to belong to the interleavingaccess area when the address input from the modem processor is less thanthe base address of the linear access area or equal to or greater than asum of the base address and the size of the linear access area.

In some embodiments, the linear access area comprises one or more linearaccess areas.

In some embodiments, the memory system further comprises a centralprocessing unit, and wherein the central processing unit, the memorycontroller, the modem processor, and the linear address remapping logicare implemented on a system-on-chip.

In some embodiments, the memory system further comprises a centralprocessing unit, and wherein the central processing unit, the memorycontroller, and the linear address remapping logic are implemented on asystem-on-chip and wherein the modern processor is implemented on amodem device.

In accordance with embodiments of the inventive concepts, a memorysystem comprises: a memory controller configured to control aninterleaving access operation on the first and second memory devices; amodem processor configured to provide an address for accessing the firstor second memory device; and linear address remapping logic configuredto receive an address from the modem processor, to remap the addressreceived from the modem processor selectively according to a controlsignal received from a central processing unit, and to provide theremapped address to the memory controller, wherein the memory controllerperforms a linear access operation on the first or second memory devicein response to the remapped address.

In some embodiments, the remapped address is partitioned into aninterleaving access area and a linear access area and wherein an addressremapping operation of the linear address remapping logic is performedby changing a location of a most significant bit of the linear accessarea,

In some embodiments, the linear address remapping logic determineswhether an address input from the modem processor belongs to the linearaccess area, based on a base address and a size of the linear accessarea.

In some embodiments, the linear address remapping logic decides theaddress input from the modem processor to belong to the linear accessarea when the address input from the modem processor is equal to orgreater than the base address of the linear access area and less than asum of the base address and the size of the linear access area.

In some embodiments, the linear address remapping logic decides theaddress input from the modem processor to belong to the interleavingaccess area when the address input from the modem processor is less thanthe base address of the linear access area or equal to or greater than asum of the base address and the size of the linear access area.

In accordance with embodiments of the inventive concepts, a memorysystem comprises: a memory controller in communication with multiplememory devices, the memory controller configured to control the multiplememory devices according to an interleaving access operation; a firstprocessor generating address signals for accessing memory locations ofthe multiple memory devices; a linear address remapping unit thatreceives the address signals, and, in response, generates remappedaddress signals; the memory controller receiving the remapped addresssignals, and, in response, controlling the multiple memory devicesaccording to a linear access operation,

In some embodiments, the memory controller, the first processor, and thelinear address remapping unit comprise a system-on-a-chip (SOC), whereinthe multiple memory devices are external to the SOC.

In some embodiments, the linear address remapping unit decides whetherto generate remapped address signals or to pass original addresssignals, in response to a control signal.

In some embodiments, the control signal is generated by a secondprocessor, wherein the first processor comprises a modem processor andwherein the second processor comprises a central processing unit (CPU).

In some embodiments, the linear address remapping unit modifies a firstportion of the original address signals that is in a linear access areaof the address signals, moves a most significant bit of the linearaccess area to a less significant bit, and shifts bits more significantthan the less significant bit in a direction toward the most significantbit to generate the remapped address signals.

In some embodiments, a second portion of the original address signalsthat is in an interleaved address area of the address signals remainsunchanged in the remapped address signals.

According to an embodiments of the inventive concepts, when theinterleaving mode is selected by CONFIG signal , at least two memoryports can write or read simultaneously larger data to and from thecorresponding memory ports to increase data band width by ignoring someILB bit in the original address. On the other hand, in linear addressingmode, only a selected port can operate and reduce power consumptioncompared with the interleaving mode.

BRIEF DESCRIPTION OF THE FIGURES

The above and other objects and features will become apparent from thefollowing description with reference to the following figures, whereinlike reference numerals refer to like parts throughout the variousfigures unless otherwise specified, and wherein

FIG. 1 is a block diagram schematically illustrating a memory systemaccording to an embodiment of the inventive concepts.

FIG. 2 is a block diagram schematically illustrating an interleavingaccess operation of a memory system of the type illustrated in FIG. 1.

FIG. 3 is a table for describing an interleaving access method accordingto an address of a memory system of the type illustrated in FIG. 1.

FIG. 4 is a block diagram schematically illustrating a memory systemthat is configured to perform a partial interleaving access operationaccording to an embodiment of the inventive concepts.

FIG. 5 is a block diagram schematically illustrating an exampleembodiment of the linear address remapping logic illustrated in FIG. 4,according to an embodiment of the inventive concepts.

FIG. 6 is a conceptual diagram illustrating a range of operatingaddresses of the linear address remapping logic of FIG. 4, according toan embodiment of the inventive concepts.

FIG. 7 is a diagram schematically illustrating an address remappingmethod of the linear address remapping logic in FIGS. 4 and 5, accordingto an embodiment of the inventive concepts.

FIG. 8 is a block diagram conceptually illustrating a partialinterleaving access operation of a memory system of the type illustratedin FIG. 4, according to an embodiment of the inventive concepts.

FIG. 9 is a flow chart for describing a partial interleaving accessoperation of a memory system of the type illustrated in FIG. 4,according to an embodiment of the inventive concepts.

FIG. 10 is a conceptual diagram illustrating an example in which twolinear access areas are present, according to an embodiment of theinventive concepts.

FIG. 11 is a block diagram for generation of a CONFIG signal controllinga remapping signal according to setting of a special function register(SFR).

FIG. 12 is a block diagram schematically illustrating a memory system inwhich a modem chip is external to, and in communication with, asystem-on-chip, according to an embodiment of the inventive concepts.

FIG. 13 is a diagram illustrating an expression of a linear accessoperation of a memory system including two or more memory devices,according to an embodiment of the inventive concepts.

DETAILED DESCRIPTION

Embodiments will be described in detail with reference to theaccompanying drawings. The inventive concepts, however, may be embodiedin various different forms, and should not be construed as being limitedonly to the illustrated embodiments. Rather, these embodiments areprovided as examples so that this disclosure will be thorough andcomplete, and will fully convey the concept of the inventive concepts tothose skilled in the art. Accordingly, known processes, elements, andtechniques are not described with respect to some of the embodiments ofthe inventive concepts. Unless otherwise noted, like reference numeralsdenote like elements throughout the attached drawings and writtendescription, and thus descriptions will not be repeated. In thedrawings, the sizes and relative sizes of layers and regions may beexaggerated for clarity.

It will be understood that, although the terms “first”, “second”,“third”, etc., may be used herein to describe various elements,components, regions, layers and/or sections, these elements, components,regions, layers and/or sections should not be limited by these terms.These terms are only used to distinguish one element, component, region,layer or section from another region, layer or section. Thus, a firstelement, component, region, layer or section discussed below could betermed a second element, component, region, layer or section withoutdeparting from the teachings of the inventive concepts.

Spatially relative terms, such as “beneath”, “below”, “lower”, “under”,“above”, “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. For example, if the device inthe figures is turned over, elements described as “below” or “beneath”or “under” other elements or features would then be oriented “above” theother elements or features. Thus, the exemplary terms “below” and“under” can encompass both an orientation of above and below. The devicemay be otherwise oriented (rotated 90 degrees or at other orientations)and the spatially relative descriptors used herein interpretedaccordingly. In addition, it will also be understood that when a layeris referred to as being “between” two layers, it can be the only layerbetween the two layers, or one or more intervening layers may also bepresent.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the inventiveconcepts. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items. Also, the term “exemplary” is intended to referto an example or illustration.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to”, “coupled to”, or “adjacent to” anotherelement or layer, it can be directly on, connected, coupled, or adjacentto the other element or layer, or intervening elements or layers may bepresent. In contrast, when an element is referred to as being “directlyon,” “directly connected to”, “directly coupled to”, or “immediatelyadjacent to” another element or layer, there are no intervening elementsor layers present.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this inventive concepts belongs.It will be further understood that terms, such as those defined incommonly used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand/or the present specification and will not be interpreted in anidealized or overly formal sense unless expressly so defined herein.

A memory system according to an embodiment of the inventive concepts mayperform an interleaving access operation in which an applicationprocessor uses two or more memory devices (e.g., DRAMs) and accessesports of the memory devices in turn. The inventive concepts may performthe interleaving access operation on two or more memory devices (e.g.,DRAMs), but may perform a linear access operation partially with respectto a specific area of a memory. Below, an interleaving access operationand a partial linear access operation of the memory system according toan embodiment of the inventive concepts will be described.

FIG. 1 is a block diagram schematically illustrating a memory systemaccording to an embodiment of the inventive concepts. Referring to FIG.1, a memory system 100 may include a first memory device 111, a secondmemory device 112, and an application processor 120 implemented on asystem-on-chip (SoC).

The application processor 120 may include a memory controller 121 tocontrol the first and second memory devices 111 and 112, a busconnection unit 122, a CPU 123, a multimedia processor 124, and a modemprocessor 125. The memory controller 121 may access the first memorydevice 111 through a first port and the second memory device 112 througha second port. The CPU 123 may control an overall operation of theapplication processor 120. Also, the CPU 123 may control peripheraldevices such as the memory devices 111 and 112. In the presentspecification, the terms “memory” and “memory device” areinterchangeable.

The multimedia processor 124 may be configured to control multimediadevices such as a camera, a display, and so on. To control themultimedia devices, the multimedia processor 124 may access the firstand second memory devices 111 and 112 connected with the applicationprocessor 120 according to an interleaving access arrangement. Forexample, the multimedia processor 124 may alternately access the firstand second memory devices 111 and 112 through the memory controller 121.

The modem processor 125 implemented on the system-on-chip may comprise aprocessor configured to perform wireless communication with a basestation or with other communication devices. The modem processor 125 mayaccess the first memory device 111 or the second memory device 112servicing the application processor 120. At this time, like themultimedia processor 124, the modem processor 125 may access both thefirst and second memory devices 111 and 112 in an interleavingarrangement. For example, the modem processor 125 may alternately accessthe first and second memory devices 111 and 112 through the memorycontroller 121.

FIG. 2 is a block diagram schematically illustrating an interleavingaccess operation of a memory system of the type illustrated in FIG. 1.Referring to FIG. 2, a memory controller 121 may receive a memory accessaddress ADDR, and, in response, perform an interleaving access operationon the first and second memory devices 111 and 112 through first andsecond ports PORT1, PORT2.

The memory controller 121 may write data to the first memory device 111through the first port or read data from the first memory device 111through the first port. The first memory device 111 may be supplied witha power and a clock for a memory access. The memory controller 121 mayaccess the second memory device 112 through the second port, The secondmemory device 112 may be supplied with a power and a clock. As describedabove, the memory controller 121 may perform an interleaving accessoperation on the first and second memory devices 111 and 112 in responseto the memory access address ADDR.

FIG, 3 is a table for describing an interleaving access method accordingto an address of a memory system of the type illustrated in FIG, 1.Referring to FIG. 3, a memory access address ADDR may include chunk bitsand an interleaving bit ILB,

In an example of FIG, 3, the chunk bits are located at theleast-significant-bit LSB side, and the interleaving bit ILB may belocated adjacent the chunk bits. A memory controller 121 (refer to FIG.2) may perform an interleaving access operation in response to the chunkunit, and may decide on whether to access memory through the first portPORT1 or a second port PORT2 (see FIG. 2) in response to theinterleaving bit ILB, As illustrated in FIG, 3, in an exampleembodiment, the first port may be selected when the interleaving bit ILBis ‘0’, and the second port may be selected when the interleaving bitILB is ‘1’,

Herein, the unit of the interleaving operation may be decided accordingto the number of chunk bits. For example, it may be assumed that 1-bytedata is stored according to an address. Under this assumption, when thenumber of chunk bits is 2, an interleaving access operation may beperformed using a 4-byte unit. When the number of chunk bits is m, theinterleaving access operation may be performed using a 2^(m)-byte unit.

Meanwhile the number of interleaving bits may be decided according tothe number of memory devices being accessed. For example, a singleinterleaving bit may be used when the number of memory devices is 2. Twointerleaving bits may be used when the number of memory devices is 4.That is, n interleaving bits may be used when the number of memorydevices is 2^(n).

In the example memory system illustrated in FIGS. 1 to 3, a modemprocessor 125 may perform an interleaving access operation with respectto first and second memory devices 111 and 112. That is, the modemprocessor 125, as illustrated in FIG. 2, may perform the interleavingaccess operation using all available memory devices, in this case, thefirst and second ports are used in turn.

In some example embodiments, a memory system according to an embodimentof the inventive concepts may support a partial interleaving accessoperation. That is, in performing the interleaving access operation onthe first and second memory devices 111 and 112, the memory system mayoptionally perform a linear access operation on the first memory device111 or the second memory device 112. On the other hand, in performing alinear access operation, the memory system may optionally perform aninterleaving access operation.

The memory system according to an embodiment of the inventive conceptsmay perform the partial interleaving access operation in variousmanners. Below, an example embodiment of a method in which the partialinterleaving access operation is performed without a change in thememory controller will be described.

FIG. 4 is a block diagram schematically illustrating a memory systemthat is configured to perform a partial interleaving access operationaccording to an embodiment of the inventive concepts. Referring to FIG.4, a memory system 200 may include a first memory 211, a second memory212, and an application processor 220 implemented on a system-on-chip(SoC).

The application processor 220 may comprise a memory controller 221, abus connection unit 222, a CPU 223, a multimedia processor 224, a firstprocessor 225, and linear address remapping logic 226. The memorycontroller 221 may access the first memory 211 via a first port PORT1and the second memory 212 via a second port PORT2.

In the memory system 200 of FIG. 4, a linear access operation may beperformed at a specific area, or in a specific address region, of thefirst and second memory devices 211 and 212 by connecting the linearaddress remapping logic 226 to the first processor 225. The inventiveconcepts may thus perform a partial interleaving access operationwithout requiring a change of the memory controller 221 by adding thelinear address remapping logic 226. In some embodiments, the firstprocessor 225 may be a modem processor.

FIG. 5 is a block diagram schematically illustrating an exampleembodiment of the linear address remapping logic illustrated in FIG. 4,according to an embodiment of the inventive concepts. Referring to FIG.5, linear address remapping logic 226 may include a first selector 11, asecond selector 12, a first remapper 21, and a second remapper 22.Herein, the first selector 11 and the first remapper 21 may be used whena write address W_ADDR is received, and the second selector 12 and thesecond remapper 22 may be used when a read address R_ADDR is received.

The linear address remapping logic 226 may receive a selection signalCONFIG from a CPU 223 (refer to FIG, 4), and, in response to the stateof the selection signal CONFIG, select whether an interleaving accessoperation or a partial linear access operation will be enabled. Forexample, when the selection signal CONFIG is 0, an address W_ADDR orR_ADDR received from a first processor 225 may be provided to a memorycontroller 221 (refer to FIG. 4). When the selection signal CONFIG is 1,an address W_ADDR′ or R_ADDR′ remapped by the first remapper 21 or thesecond remapper 22 may be provided to the memory controller 221.Described below is an example in which the linear address remappinglogic 226 selects the partial linear access operation.

FIG. 6 is a conceptual diagram illustrating a range of operatingaddresses of the linear address remapping logic of FIG. 4, according toan embodiment of the inventive concepts. Referring to FIG. 6, a memoryaccess address may be partitioned or divided into an interleaving accessarea IAA, including memory addresses designated for an interleavingaccess operation to be performed and a linear access area LAA, includingmemory addresses designated for a linear access operation to beperformed.

In FIG. 6, the interleaving access operation may be performed atinterleaving access areas IAA respectively defined within addresses (A1and A2) and within addresses (A3 and A4). Herein, an address range wherelinear address remapping logic 226 (refer to FIG. 4) operations may bedefined within addresses A2 and A3. Herein, the address A2 may be an LAAbase address, and the address A3 may be an address defined by (LAA baseaddress+LAA size−1). The linear address remapping logic 226 may receivethe LAA base address and the LAA size as configuration values foroperation of the LAA.

FIG. 7 is a diagram schematically illustrating an address remappingmethod of the linear address remapping logic in FIGS. 4 and 5, accordingto an embodiment of the inventive concepts. In FIG. 7, an originaladdress may be an address W_ADDR or R_ADDR as provided to linear addressremapping logic 226 from a first processor 225 (refer to the example ofFIG. 4). A remapped address may be an address W_ADDR′ or R_ADDR′ asremapped by the linear address remapping logic 226.

Referring to FIG. 7, a memory access address ADDR may include chunk bitsand an interleaving bit ILB. Chunk bits may indicate an execution unitof an interleaving access operation, and the interleaving bit ILB orbits may be used to decide which memory port is to be accessed; in thepresent example, whether a first port or a second port is to beaccessed. The LAA bits may indicate an address in the address rangewhere a linear access operation is to be performed, and an IAA bits mayindicate an address in the address range where an interleaving accessoperation is to be performed.

The linear address remapping logic 226 may perform a remapping operationusing an LAA size MSB of the linear address. For example, in the casethat the LAA size is 64 megabytes, a 26^(th) bit (log2(26)) being a bitcorresponding to log2(LAA size) may be moved to the position of theinterleaving bit of the remapped ADDR. Any remaining bits of theremapped

ADDR more significant than the interleaving bit or bits are shifted inthe direction of the MSB as shown. The interleaving bit ILB and the LAAbits are shifted to the left, while the IAA bits remain in theirpositions.

In the above description, an interleaving bit corresponding to thelinear access area LAA may be made to have the same value (0 or 1), sothat a linear access operation can be performed in a situation whichotherwise would have led to an interleaved operation. In the presentexample embodiment, the linear address remapping logic 226 uses the LAAsized MSB of the original address as the interleaving bit in theremapped address. However, the inventive concepts are not limitedthereto. It is possible to perform a remapping operation using othersuitable approaches.

FIG. 8 is a block diagram conceptually illustrating a partialinterleaving access operation of a memory system of the type illustratedin FIG. 4, according to an embodiment of the inventive concepts.Referring to FIG. 8, a memory controller 221 may receive one or moreremapped addresses that cause it to perform a partial interleavingaccess operation on first and second memory devices 211 and 212 viafirst and second ports.

In the present example embodiment, at certain times in its operation,the memory controller 221 may alternately access the first and secondmemory devices 211 and 212 through the first and second ports during anIAA period. That is, an interleaving access operation on the first andsecond memory devices 211 and 212 may be performed. At other times inits operation, the memory controller 221 may perform a linear accessoperation on the first memory 211 via the first port during an LAAperiod. If the linear access operation on the first memory 211 iscompleted, for example, if the upper memory address of the LAA region ofthe first memory device 211 has been reached, the memory controller 221may continue the linear access operation on the second memory 212 viathe second port. In another operation, the memory controller 221 mayalternately access the first and second memory devices 211 and 212through the first and second ports during an IAA period. In this manner,an interleaving access operation on the first and second memory devices211 and 212 may be performed as well as a linear access operation. Thusthe memory system has a partial interleaving access operation capabilityin connection with the present inventive concepts.

FIG. 9 is a flow chart for describing a partial interleaving accessoperation of a memory system of the type illustrated in FIG. 4,according to an embodiment of the inventive concepts.

A partial interleaving access operation of a memory system will now bemore fully described with reference to FIGS. 4 to 9.

In operation S110, a memory access address may be received. Linearaddress remapping logic 226 may have information pertaining to a baseaddress and a size of a linear access area LAA. The linear addressremapping logic 226 may decide whether the input memory access addressbelongs to an interleaving access area IAA or a linear access area LAA,based on the LAA base address and the LAA size.

In operation S120, the linear address remapping logic 226 may determinewhether the memory access address is larger than the LAA base address.If the memory access address is less than the LAA base address, inoperation S155, an interleaving access operation may be performed. Ifthe memory access address is equal to or larger than the LAA baseaddress, the method proceeds to operation S130.

In operation S130, the linear address remapping logic 226 may determinewhether the memory access address is less than (LAA base address+LAAsize). If not, in operation S155, the interleaving access operation maybe performed. If so, the method proceeds to operation S140.

In operation S140, the linear address remapping logic 226 may performlinear address remapping. With the linear address remapping, asdescribed with reference to FIG. 7, an LAA size MSB may be move to theposition of an interleaving bit, and remaining upper bits of the LAA maybe shifted in the direction of the MSB.

In operation S150, a memory controller 221 may receive a remappedaddress to perform a linear access operation on a first memory 211 or asecond memory 212 at address LAA.

In operation S155, in a case where an interleaved access operation is tobe performed, the memory controller 221 may perform the interleavingaccess operation on the first and second memory devices 211 and 212 ataddress IAA.

A memory system 200 according to an embodiment of the inventive conceptsmay determine whether a memory access address belongs to a linear accessarea LAA, through operations S120 and S130. As illustrated in FIG. 6, ina case where the memory access address belongs to an interleaving accessarea IAA (A1˜A2, A3˜A4), the interleaving access operation may beperformed. In a case where the memory access address belongs to a linearaccess area LAA (A2˜A3), the linear access operation may be performed.

Meanwhile, a memory system according to an embodiment of the inventiveconcepts is applicable to a case where two or more linear access areasLAA exist in the thus-partitioned memory device. FIG. 10 is a conceptualdiagram illustrating an example in which two linear access areas arepresent, according to an embodiment of the inventive concepts.

In FIG. 10, an interleaving access operation may be performed byaccessing addresses within interleaving access areas IAA respectivelydefined by addresses intervals B1˜B2, B3˜B4, and B5˜B6, and a linearaccess operation may be performed by accessing addresses at linearaccess areas LAA respectively defined by address intervals B2˜B3 andB4˜B5.

Herein, linear address remapping logic 226 (refer to FIG. 4) may operateaddress ranges B2˜B3 and B4˜B5 as illustrated in FIG. 10. Herein, eachof the addresses B2 and B4 may comprise an LAA base address, and each ofthe addresses B3 and B5 may comprise (LAA base address+LAA size−1). Thelinear address remapping logic 226 may receive the LAA base address andthe LAA size as configuration values to operate the partitioning of thememory device to include and define the LAA. Returning to FIG. 4, thelinear address remapping logic 226 can be connected to a CPU 223 or amultimedia processor 224 in such a manner that the linear addressremapping logic 226 is connected to the first processor 225. Also, thelinear address remapping logic 226 can be connected to share processorssuch as the CPU 223, the multimedia processor 224, and the firstprocessor 225.

FIG. 11 is a block diagram for generation of a CONFIG signal controllinga remapping signal according to setting of a special function register(SFR). LAA1 Stat may be a start address of a first area for a linearaccess, and LAA1 size may indicate a size of the LAA1 area. LAA2 Statmay be a start address of a second area for a linear access, and LAA2size may indicate a size of the LAA2 area. A special function register(SFR) may be set by a CPU. The special function register (SFR) may becompared with a memory access address. When the memory access addressbelongs to the LAA1 or LAA2, a signal CONFIG may be activated such thata remapping address is selected.

Although the above example embodiment illustrates a memory systemincluding a modem chip that is integrated with the memory system on thesame system-on-chip (SoC), the memory system according to the inventiveconcepts is equally applicable to a case where a modem chip is externalto the system-on-chip (SoC). In this case, the modem chip and thesystem-on-chip may be interconnected via a chip-to-chip (C2C) interface.

FIG. 12 is a block diagram schematically illustrating a memory system inwhich a modem chip is external to, and in communication with, asystem-on-chip, according to an embodiment of the inventive concepts.Referring to FIG. 12, a memory system 300 may include a first memory311, a second memory 312, an application processor 320 implemented on asystem-on-chip (SoC), and a modem chip 330.

The application processor 320 may include a memory controller 321, a busconnection unit 322, a CUP 323, a multimedia processor 324, and linearaddress remapping logic 326. The memory controller 321 may access thefirst memory 311 via a first port and the second memory 312 via a secondport.

In the memory system 300 of FIG. 12, a linear access operation may beperformed at a specific area of the first and second memory devices 311and 312 by connecting the linear address remapping logic 326 to themodem chip 330. The inventive concepts may perform a partialinterleaving access operation without requiring a change of the memorycontroller 321 by including the linear address remapping logic 326. InFIG. 12, the linear address remapping logic 326 can be placed betweenthe bus connection unit 322 and the memory controller 321.

As described above, a memory system according to an embodiment of theinventive concepts may perform an interleaving access operation or apartial linear access operation with respect to two or more memorydevices. It is possible to use memory devices effectively by adjusting abandwidth balance among two or more memory devices through aninterleaving access operation.

Meanwhile, in the case of the memory dynamics required when using amodem, the memory demands are such that there is no need to performinterleaving access with respect to multiple memory devices. In thiscase, the inventive concepts may employ a linear access operation. Inparticular, the inventive concepts may be efficiently used in mobilesystems requiring reduced power consumption. The inventive concepts mayperform a partial linear access operation in a memory system using aninterleaving access operation. Thus, it is possible to use only a singlememory or to intentionally focus a memory bandwidth onto a single memoryin situations where such an arrangement is advantageous.

The inventive concepts may enable clock gating or power gating ofanother memory which is at an idle state. Power consumption may bereduced by inducing the memory into a self-refresh mode. If aninterleaving access operation is applied to the whole of memories, apower and a clock may be continuously supplied to the whole of thememory devices. Thus, power consumption may increase.

In a memory system using an interleaving access operation, the inventiveconcepts may perform a partial linear access operation by includinglinear access remapping logic at a front stage of a specific processor(e.g., modem). In this manner, power consumption can be reduced forprocessors or for processor operations that do not require theperformance gains that otherwise would be realized by use of aninterleaved access arrangement.

FIG. 13 is a diagram illustrating an expression of a linear accessoperation of a memory system including two or more memory devices,according to an embodiment of the inventive concepts.

In FIG. 13, ‘a_(n)’, ‘IVsize’, and ‘IVport’ may indicate an base addressof an nth chuck, a chunk size, the number of memory ports (0, 1, 2, . .. , port), respectively.

Since a memory access address ‘a’ is divided into an nth base address‘a_(n)’ and an offset address ‘a_(off)’, the memory access address a maybe expressed by the following equation 1.

a=a _(n) +a _(off)   [Equation 1]

In the equation 1, since a chuck size is IVsize, 0=<aoff<IVsize. In theequation 1, ‘a_(n)’ may indicate a value of an address area increasedfrom a base address ‘a₀’ of a first chunk by a chunk number, and may beexpressed by the following equation 2.

$\begin{matrix}{{a_{n} = {a_{0} + {{/V_{SIZE}} \times n}}}{n = \frac{a_{n} - a_{0}}{/V_{SIZE}}}} & \left\lbrack {{Equation}\mspace{14mu} 2} \right\rbrack\end{matrix}$

It is assumed that a chunk is selected in consideration of interleaving.If there is selected a memory chunk corresponding to an rth port of oneor more memory ports and there is selected a kth memory chunk from thelowermost stage at each memory port, ‘a_(n)’ may be expressed asfollows.

a _(n) =a _((r,k)) =a _(IVport×k×r) =a ₀ IV _(SIZE)×(IVport×k+r)=a ₀ +IV_(size) ×IVport×k+IV _(size) ×r   [Equation 3]

In the equation 3, ‘r’ may indicate a value for selecting a row, ‘k’ mayindicate a value for selecting a column, and 0≦r≦IVport.

Thus, as described with reference to FIGS. 7 and 8, a chunk bitdescribed in FIG. 7 may correspond to ‘a_(off)’, ILB of an originaladdress may correspond to a ‘r’ value of the equation 3 selecting amemory port, and IAA and LAA bits may correspond to a ‘k’ value. It ispossible to generate an address for accessing each memory port using abit of an original address. As described with reference to FIG. 7, it ispossible to remap a linear address partially by handling LAA and ILBbits.

According to an embodiments of the inventive concepts, when theinterleaving mode is selected by CONFIG signal, at least two memoryports can write or read simultaneously larger data to and from thecorresponding memory ports to increase data band width by ignoring someILB bit in the original address in FIG. 3. On the other hand, in linearaddressing mode, only a selected port can operate and reduce powerconsumption compared with the interleaving mode.

A memory system according to an embodiment of the inventive concepts maybe applied to various products. For example, the memory system accordingto an embodiment of the inventive concepts may be applied to a digitalcamera, a camcorder, a mobile phone, a smart phone, a digital TV, a PMP,a PSP, a PDA, and other mobile devices.

A memory system according to an embodiment of the inventive concepts maybe packed by a variety of packages such as PoP (Package on Package),Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded ChipCarrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack,Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package(CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack(TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), ThinSmall Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP),Wafer-level Fabricated Package (WFP), Wafer-Level Processed StackPackage (WSP), and other types of packages.

While the inventive concepts have been described with reference toexemplary embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the present specification. Therefore, itshould be understood that the above embodiments are not limiting, butrather are illustrative.

1. (canceled) .
 2. A memory channel interleaving method for a powerreduction or a performance improvement, the method comprising: remappinga memory access address for two or more memory devices accessed via twoor more respective memory ports with an interleaving access area and alinear access area, the interleaving access area comprising memoryaddresses for an interleaving access operation for the performanceimprovement, the linear access area comprising memory addresses for alinear access operation for the power reduction; receiving a signal thatincludes a power reduction mode or a performance improvement mode; andperforming the interleaving access operation or the linear accessoperation according to the performance improvement mode or the powerreduction mode.
 3. The method of claim 2, wherein the linear access areacomprises a first address range associated with a first memory deviceamong the two or more memory devices and accessed via a first port amongthe two or more memory ports, and a second address range associated witha second memory device among the two or more memory devices and accessedvia a second port among the two or more memory ports.
 4. The method ofclaim 3, wherein the performing the linear access operation comprisesusing the first address range associated with the first memory devicewhile the second memory device is placed in the power reduction mode. 5.The method of claim 4, further comprising when a last memory address inthe first address range of the linear access area is reached: placingthe first memory device in the power reduction mode; activating thesecond memory device; and performing the linear access operation in thepower reduction mode for the second address range associated with thesecond memory device.
 6. The method of claim 2, wherein the linearaccess operation is performed in the linear access area with a firstmemory device among the two or more memory devices activated and asecond memory device among the two or more memory devices placed in thepower reduction mode.
 7. The method of claim 2, wherein the powerreduction mode or the performance improvement mode is specified by thesignal to a linear address remapping logic.
 8. The method of claim 2,wherein the interleaving access area or the linear access area comprisesa bit specifying a memory device.
 9. The method of claim 2, wherein thetwo or more memory devices comprise dynamic random access memory (DRAM)devices.
 10. The method of claim 2, wherein a memory controller receivesthe signal that includes the power reduction mode or the performanceimprovement mode via a bus connection unit.
 11. The method of claim 2,further comprising adjusting a bandwidth balance among the two or morememory devices through the interleaving access operation.
 12. The methodof claim 2, wherein when a memory dynamics is required, the linearaccess operation is performed.
 13. A memory channel interleaving systemfor a power reduction or a performance improvement, the systemcomprising: a linear address remapping logic configured to remap amemory access address for two or more memory devices accessed via two ormore respective memory ports with an interleaving access area and alinear access area, the interleaving access area comprising memoryaddresses for an interleaving access operation for the performanceimprovement, the linear access area comprising memory addresses for alinear access operation for the power reduction, a linear addressremapping logic being configured to receive a signal that includes apower reduction mode or a performance improvement mode; and a memorycontroller configured to perform the interleaving access operation orthe linear access operation according to the performance improvementmode or the power reduction mode.
 14. The system of claim 13, whereinthe linear access area comprises a first address range associated with afirst memory device among the two or more memory devices and accessedvia a first port among the two or more memory ports, and a secondaddress range associated with a second memory device among the two ormore memory devices and accessed via a second port among the two or morememory ports.
 15. The system of claim 14, wherein the memory controlleris configured to use the first address range associated with the firstmemory device while the second memory device is placed in the powerreduction mode.
 16. The system of claim 15, wherein when a last memoryaddress in the first address range of the linear access area is reached,the memory controller is configured to: place the first memory device inthe power reduction mode; activate the second memory device; and performthe linear access operation in the power reduction mode for the secondaddress range associated with the second memory device.
 17. The systemof claim 13, wherein the linear access operation is performed in thelinear access area with a first memory device among the two or morememory devices activated and a second memory device among the two ormore memory devices placed in the power reduction mode.
 18. The systemof claim 13, wherein the power reduction mode or the performanceimprovement mode is specified by the signal to the linear addressremapping logic.
 19. The system of claim 13, wherein the interleavingaccess area or the linear access area comprises a bit specifying amemory device.
 20. The system of claim 13, wherein the two or morememory devices comprise dynamic random access memory (DRAM) devices. 21.The system of claim 13, wherein the memory controller receives thesignal that includes the power reduction mode or the performanceimprovement mode via a bus connection unit.
 22. The system of claim 13,wherein a bandwidth balance among the two or more memory devices isadjusted through the interleaving access operation.
 23. The system ofclaim 13, wherein when a memory dynamics is required, the linear accessoperation is performed.
 24. A system for providing a memory channelinterleaving for a power reduction or a performance improvement, thesystem comprising: a system on chip (SOC) comprising linear addressremapping logic configured to remap a memory access address for two ormore memory devices accessed via two or more respective memory portswith an interleaving access area and a linear access area, theinterleaving access area comprising memory addresses for an interleavingaccess operation for the performance improvement, the linear access areacomprising memory addresses for a linear access operation for the powerreduction, a linear address remapping logic being configured to receivea signal that includes a power reduction mode or a performanceimprovement mode; and a memory controller residing on the SoC andconfigured to perform the interleaving access operation or the linearaccess operation according to the performance improvement mode or thepower reduction mode.
 25. The system of claim 24, wherein the linearaccess area comprises a first address range associated with a firstmemory device among the two or more memory devices and accessed via afirst port among the two or more memory ports, and a second addressrange associated with a second memory device among the two or morememory devices and accessed via a second port among the two or morememory ports.
 26. The system of claim 25, wherein the memory controlleris configured to use the first address range associated with the firstmemory device while the second memory device is placed in the powerreduction mode.
 27. The system of claim 26, wherein when a last memoryaddress in the first address range of the linear access area is reached,the memory controller is configured to: place the first memory device inthe power reduction mode; activate the second memory device; and performthe linear access operation in the power reduction mode for the secondaddress range associated with the second memory device.
 28. The systemof claim 24, wherein the linear access operation is performed in thelinear access area with a first memory device among the two or morememory devices activated and a second memory device among the two ormore memory devices placed in the power reduction mode.
 29. The systemof claim 24, wherein the power reduction mode or the performanceimprovement mode is specified by the signal to the linear addressremapping logic.
 30. The system of claim 24, wherein the interleavingaccess area or the linear access area comprises a bit specifying amemory device.
 31. The system of claim 24, wherein the two or morememory devices comprise dynamic random access memory (DRAM) devices. 32.The system of claim 24, wherein the SOC resides on a portablecommunications device.
 33. The system of claim 24, wherein a bandwidthbalance among the two or more memory devices is adjusted through theinterleaving access operation.
 34. The system of claim 24, wherein whena memory dynamics is required, the linear access operation is performed.